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Integrated Circuit Systems, Inc.
ICS87608I
LOW VOLTAGE/LOW SKEW, 1:8 PCI/PCI-X ZERO DELAY CLOCK GENERATOR
FEATURES
* Fully integrated PLL * 8 LVCMOS/LVTTL outputs, 15 typical output impedance * Selectable crystal oscillator interface or LVCMOS/LVTTL REF_IN clock input * Maximum output frequency: 166.67MHz * Maximum crystal input frequency: 38MHz * Maximum REF_IN input frequency: 41.67MHz * Individual banks with selectable output dividers for generating 33.333MHz, 66.66MHz, 100MHz and 133.333MHz * Separate feedback control for generating PCI / PCI-X frequencies from a 16.66MHz or 20MHz crystal, or 25MHz or 33.33MHz reference frequency * VCO range: 200MHz to 500MHz * Cycle-to-cycle jitter: 120ps (maximum), @ 3.3V * Period jitter, RMS: 20ps (maximum) * Output skew: 250ps (maximum) * Bank skew: 60ps (maximum) * Static phase offset: 160ps 160ps * Voltage Supply Modes: VDD (core/inputs), VDDA (analog supply for PLL), VDDOA (output bank A), VDDOB (output bank B, REF_OUT, FB_OUT) VDD/VDDA/VDDOA/VDDOB 3.3/3.3/3.3/3.3 3.3/3.3/2.5/3.3 3.3/3.3/3.3/2.5 3.3/3.3/2.5/2.5 * Lead-Free package fully RoHS compliant * -40C to 85C ambient operating temperature
VDDOB
GENERAL DESCRIPTION
The ICS87608I has a selectable REF_CLK or crystal input. The REF_CLK input accepts HiPerClockSTM LVCMOS or LVTTL input levels. The ICS87608I has a fully integrated PLL along with frequency configurable clock and feedback outputs for multiplying and regenerating clocks with "zero delay".
ICS
The ICS87608I is a 1:8 PCI/PCI-X Clock Generator and a member of the HiPerClockSTM family of high performance clock solutions from ICS. The ICS87608I has a selectable REF_CLK or crystal input. The REF_CLK input accepts LVCMOS or LVTTL input levels. The ICS87608I has a fully integrated PLL along with frequency configurable clock and feedback outputs for multiplying and regenerating clocks with "zero delay". The PLL's VCO has an operating range of 250MHz-500MHz, allowing this device to be used in a variety of general purpose clocking applications. For PCI/PCI-X applications in particular, the VCO frequency should be set to 400MHz. This can be accomplished by supplying 33.33MHz, 25MHz, 20MHz, or 16.66MHz on the reference clock or crystal input and by selecting /12, /16, /20, or /24, respectively as the feedback divide value. The dividers on each of the two output banks can then be independently configured to generate 33.33MHz (/12), 66.66MHz (/6), 100MHz (/4), or 133.33MHz (/3). The ICS87608I is characterized to operate with its core supply at 3.3V and each bank supply at 3.3V or 2.5V. The ICS87608I is packaged in a small 7x7mm body LQFP, making it ideal for use in space-constrained applications.
PIN ASSIGNMENT
REF_IN VDDOA XTAL2 XTAL1
32 31 30 29 28 27 26 25 QA0 QA1 GND QA2 QA3 VDDOA MR DIV_SELA0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
DIV_SELA1 DIV_SELB0 DIV_SELB1 FBDIV_SEL0 FBDIV_SEL1 VDD FB_IN GND
ICS87608I
32-Lead LQFP 7mm x 7mm x 1.4mm package body Y package Top View
XTAL_SEL
PLL_SEL
VDDA
24 23 22 21 20 19 18 17
QB0 QB1 GND QB2 QB3 VDDOB REF_OUT FB_OUT
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Integrated Circuit Systems, Inc.
ICS87608I
LOW VOLTAGE/LOW SKEW, 1:8 PCI/PCI-X ZERO DELAY CLOCK GENERATOR
BLOCK DIAGRAM
DIV_SELA0 DIV_SELA1
XTAL_SEL
/3 00 01 10 11
QA0 QA1 QA2 QA3
REF_IN XTAL1 OSC XTAL2
0 1 PLL
0 1
/4 /6 /12
FB_IN QB0 QB1 QB2 QB3
PLL_SEL
00 01 10 11
D_SELB1 D_SELB0
/12 /16 /20 /24
00 01 10 11
REF_OUT FB_OUT
FBDIV_SEL1 FBDIV_SEL0 MR
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Integrated Circuit Systems, Inc.
ICS87608I
LOW VOLTAGE/LOW SKEW, 1:8 PCI/PCI-X ZERO DELAY CLOCK GENERATOR
Type Output Power Power Input Description Bank A clock outputs. 15 typical output impedance. LVCMOS / LVTTL interface levels. Power supply ground.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2, 4, 5 3, 16, 22 6, 32 7 8, 9, 10, 11 12, 13 14 15 17 18 19, 25 20, 21, 23, 24 26 27 28 29, 30 31 Name QA0, QA1, QA2, QA3 GND VDDOA MR DIV_SELA0, DIV_SELA1, DIV_SELB0, DIV_SELB1 FBDIV_SEL0, FBDIV_SEL1 VDD FB_IN FB_OUT REF_OUT VDDOB QB3, QB2, QB1, QB0 PLL_SEL VDDA XTAL_SEL XTAL1, XTAL2 REF_IN
Output supply pins for Bank A outputs. Active HIGH Master Reset. When logic HIGH, the internal dividers Pulldown are reset causing the outputs go low. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. Pulldown Selects divide value for clock outputs as described in Table 3. LVCMOS / LVTTL interface levels.
Input
Input Power Input Output Output Power Output Input Power Input Input Input
Selects divide value for reference clock output and feedback output. LVCMOS / LVTTL interface levels. Core supply pin. Feedback input to phase detector for generating clocks with Pulldown "zero delay". LVCMOS / LVTTL interface levels. Feedback output. Connect to FB_IN. LVCMOS / LVTTL interface levels. Pulldown Reference clock output. LVCMOS / LVTTL interface levels. Output supply pins for Bank B and REF_OUT, FB_OUT outputs. Bank B clock outputs. 15 typical output impedance. LVCMOS / LVTTL interface levels. Selects between PLL and bypass mode. When HIGH, selects PLL. When LOW, selects reference clock. LVCMOS / LVTTL interface levels. Analog supply pin. See Applications Note for filtering. Selects between cr ystal oscillator or reference clock as the PLL reference source. Selects XTAL inputs when HIGH. Selects REF_IN when LOW. LVCMOS / LVTTL interface levels. Cr ystal oscillator interface. XTAL1 is the input. XTAL2 is the output. Pulldown Reference clock input. LVCMOS / LVTTL interface levels.
Pullup
Pullup
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN CPD ROUT Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output); NOTE 1 Output Impedance VDD, VDDA, VDDOX = 3.465V VDD, VDDA = 3.465V; VDDOX = 2.625V 15 Test Conditions Minimum Typical 4 51 51 9 11 Maximum Units pF k k pF pF
VDDOX denotes VDDOA and VDDOB.
87608AYI
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REV. B MARCH 11, 2005
Integrated Circuit Systems, Inc.
ICS87608I
LOW VOLTAGE/LOW SKEW, 1:8 PCI/PCI-X ZERO DELAY CLOCK GENERATOR
TABLE 3A. OUTPUT CONTROL PIN FUNCTION TABLE
Inputs MR 1 0 QA0:QA3 LOW Active Outputs QB0:QB3, FB_OUT, REF_OUT LOW Active
TABLE 3B. OPERATING MODE FUNCTION TABLE
Inputs PLL_SEL 0 1 Operating Mode Bypass PLL
TABLE 3C. PLL INPUT FUNCTION TABLE
Inputs XTAL_SEL 0 1 PLL Input REF_IN XTAL Oscillator
TABLE 3D. CONTROL FUNCTION TABLE
Inputs FBDIV_ SEL1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FBDIV_ SEL0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
Bank B Bank B Bank A Bank A
Outputs PLL_SEL =1 DIV_ SELA0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Reference Frequency Range (MHz) 16.67 - 41.67 16.67 - 41.67 16.67 - 41.67 16.67 - 41.67 12.5 - 31.25 12.5 - 31.25 12.5 - 31.25 12.5 - 31.25 10 - 25 10 - 25 10 - 25 10 - 25 8.33 - 20.83 8.33 - 20.83 8.33 - 20.83 8.33 - 20.83 QX0:QX3 x4 x3 x2 x1 x 5.33 x4 x 2.667 x 1.33 x 6.667 x5 x 3.33 x 1.66 x8 x6 x4 x2 Frequency QX0:QX3 (MHz) 66.68 - 166.68 50 - 125 33.34 - 83.34 16.67 - 41.67 66.63 - 166.56 50 - 125 33.34 - 83.34 16.63 - 41.56 66.67 - 166.68 50 - 125 33.30 - 83.25 16.60 - 41.50 66.64 - 166.64 50 - 125 33.32 - 83.32 16.66 - 41.66 FB_OUT (MHz) 16.67 - 41.67 16.67 - 41.67 16.67 - 41.67 16.67 - 41.67 12.5 - 31.25 12.5 - 31.25 12.5 - 31.25 12.5 - 31.25 10 - 25 10 - 25 10 - 25 10 - 25 8.33 - 20.83 8.33 - 20.83 8.33 - 20.83 8.33 - 20.83
DIV_ SELB1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
DIV_ SELB0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
DIV_ SELA1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
NOTE: VCO frequency range for all configurations above is 200MHz to 500MHz.
87608AYI
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REV. B MARCH 11, 2005
Integrated Circuit Systems, Inc.
ICS87608I
LOW VOLTAGE/LOW SKEW, 1:8 PCI/PCI-X ZERO DELAY CLOCK GENERATOR
4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 47.9C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDOX = 3.3V5% OR 2.5V5%, TA = -40C TO 85C
Symbol VDD VDDA VDDOX IDD IDDA IDDOA IDDOB Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 3.465 3.465 185 15 20 20 Units V V V mA mA mA mA
VDDOX denotes VDDOA, VDDOB.
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDOX = 3.3V5% OR 2.5V5%, TA = -40C TO 85C
Symbol Parameter MR, DIV_ SELx0, DIV_SELx1, FBDIV_SEL0, FBDIV_SEL1, Input High Voltage XTAL_SEL, FB_IN, PLL_SEL REF_IN MR, DIV_ SELx0, DIV_SELx1, FBDIV_SEL0, FBDIV_SEL1, Input Low Voltage XTAL_SEL, FB_IN, PLL_SEL REF_IN DIV_ SELx0, DIV_SELx1, FBDIV_SEL0, FBDIV_SEL1, Input High Current MR, FB_IN XTAL_SEL, PLL_SEL DIV_ SELx0, DIV_SELx1, FBDIV_SEL0, FBDIV_SEL1, Input MR, FB_IN Low Current XTAL_SEL, PLL_SEL Output High Voltage; NOTE 1 Test Conditions Minimum 2 2 -0.3 -0.3 VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V VDD = VIN = 3.465V VDD = VIN = 2.625V -5 -150 2.6 1.8 0.5 Typical Maximum VDD + 0.3 VDD + 0.3 0.8 1.3 150 5 Units V V V V A A A A V V V
VIH
VIL
IIH
IIL
VOH
Output Low Voltage; NOTE 1 VOL NOTE 1: Outputs terminated with 50 to VDDOX/2. See Parameter Measurement Information section, "3.3V Output Load Test Circuit".
87608AYI
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REV. B MARCH 11, 2005
Integrated Circuit Systems, Inc.
ICS87608I
LOW VOLTAGE/LOW SKEW, 1:8 PCI/PCI-X ZERO DELAY CLOCK GENERATOR
Test Conditions Minimum 10 7 Typical Maximum 38 50 Units MHz pF
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance
Fundamental
TABLE 6. PLL INPUT REFERENCE CHARACTERISTICS, VDD = VDDA = VDDOX = 3.3V5%, TA = -40C TO 85C
Symbol fREF Parameter Reference Frequency Test Conditions Minimum 8.33 Typical Maximum 41.67 Units MHz
TABLE 7A. AC CHARACTERISTICS, VDD = VDDA = VDDOX = 3.3V5%, TA = -40C TO 85C
Symbol fMAX t(O) t sk(b) t sk(o) Parameter Output Frequency Static Phase Offset; NOTE 1 Bank Skew; NOTE 2, 6 Output Skew; NOTE 3, 6 Cycle-to-Cycle Jitter; 6 Period Jitter, RMS; NOTE 4, 6, 7 Slew Rate PLL Lock Time Output Rise/Fall Time 20% to 80% 200 1 FREF = 25MHz 0 160 Test Conditions Minimum Typical Maximum 166.67 325 60 250 120 20 4 10 700 Units MHz ps ps ps ps ps v/ns ms ps
tjit(cc) tjit(per) t sl(o)
tL t R / tF
odc Output Duty Cycle; NOTE 5 48 52 % All parameters measured with feedback and output dividers set to DIV by 12 unless otherwise noted. NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. Measured at VDD/2. NOTE 2: Defined as skew within a bank of outputs at the same voltages and with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDOX/2. NOTE 4: Jitter performance using LVCMOS inputs. NOTE 5: Measured using REF_IN. For XTAL input, refer to Application Note. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65. NOTE 7: This parameter is defined as an RMS value.
TABLE 7B. AC CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDOX = 2.5V5%, TA = -40C TO 85C
Symbol fMAX t(O) Parameter Output Frequency Static Phase Offset; NOTE 1 Bank Skew; NOTE 2, 6 Output Skew; NOTE 3, 6 Cycle-to-Cycle Jitter; 6 Period Jitter, RMS; NOTE 4, 6, 7 Slew Rate PLL Lock Time Output Rise/Fall Time 20% to 80% 200 48
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Test Conditions FREF = 25MHz
Minimum -365
Typical -105
Maximum 166.67 160 60 250 170 20
Units MHz ps ps ps ps ps v/ns ms ps %
t sk(b) t sk(o) tjit(cc) tjit(per) tsl(o)
tL t R / tF
1
4 10 700 52
odc Output Duty Cycle; NOTE 5 See Table 7A for notes.
87608AYI
REV. B MARCH 11, 2005
Integrated Circuit Systems, Inc.
ICS87608I
LOW VOLTAGE/LOW SKEW, 1:8 PCI/PCI-X ZERO DELAY CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
1.65V5% 2.05V5% 1.25V5%
VDD, VDDA,VDDOX
SCOPE
Qx
VDD, VDDA
SCOPE
VDDOX GND
Qx
LVCMOS
GND
LVCMOS
-1.65V5%
-1.25V5%
3.3V OUTPUT LOAD AC TEST CIRCUIT
(Where X denotes outputs in the same Bank)
3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT
V
DDOX
Qx
2
Qx
VDDOX 2
V
DDOX
Qy
2 tsk(o)
Qy
tsk(b)
VDDOX 2
OUTPUT SKEW
BANK SKEW
V
DDOX
V
DDOX
V
DDOX
VDD
QAx, QBx QAx, QBx, FB_OUT, REF_OUT
87608AYI
2
2
2
REF_IN
2
tcycle
n
t(O)
1000 Cycles
CYCLE-TO-CYCLE JITTER
VDDOX 2 t PW t PERIOD VDDOX 2 VDDOX 2
STATIC PHASE OFFSET
Clock Outputs
20% tR tF
odc =
t PW t PERIOD
OUTPUT PULSE WIDTH/PULSE WIDTH PERIOD
OUTPUT RISE/FALL TIME
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tjit(cc) = tcycle n -tcycle n+1
tcycle n+1
FB_IN
VDD 2
80%
80% 20%
Integrated Circuit Systems, Inc.
ICS87608I
LOW VOLTAGE/LOW SKEW, 1:8 PCI/PCI-X ZERO DELAY CLOCK GENERATOR APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS87608I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDOX should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA.
3.3V VDD .01F V DDA .01F 10 F 10
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS87608I has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the frequency ppm error. The optimum C1 and C2 values can be slightly adjusted for optimum frequency accuracy.
XTAL2 C1 22p X1 18pF Parallel Cry stal XTAL1 C2 22p
Figure 2. CRYSTAL INPUt INTERFACE
87608AYI
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REV. B MARCH 11, 2005
Integrated Circuit Systems, Inc.
ICS87608I
LOW VOLTAGE/LOW SKEW, 1:8 PCI/PCI-X ZERO DELAY CLOCK GENERATOR RELIABILITY INFORMATION
TABLE 8. JAVS. AIR FLOW TABLE
FOR
32 LEAD LQFP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87608I is: 5495
87608AYI
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REV. B MARCH 11, 2005
Integrated Circuit Systems, Inc.
ICS87608I
LOW VOLTAGE/LOW SKEW, 1:8 PCI/PCI-X ZERO DELAY CLOCK GENERATOR
32 LEAD LQFP
PACKAGE OUTLINE - Y SUFFIX
FOR
TABLE 9. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc 0.45 0 --0.05 1.35 0.30 0.09 MINIMUM NOMINAL 32 --1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 --0.75 7 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
87608AYI
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REV. B MARCH 11, 2005
Integrated Circuit Systems, Inc.
ICS87608I
LOW VOLTAGE/LOW SKEW, 1:8 PCI/PCI-X ZERO DELAY CLOCK GENERATOR
Marking ICS87608AYI ICS87608AYI Package 32 Lead LQFP 32 Lead LQFP 32 Lead Lead-Free LQFP 32 Lead Lead-Free LQFP Shipping Packaging tray 1000 tape & reel tray 1000 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
TABLE 10. ORDERING INFORMATION
Part/Order Number ICS87608AYI ICS87608AYIT ICS87608AYILF ICS87608AYILFT
ICS87608AYIL ICS87608AYIL
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 87608AYI
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REV. B MARCH 11, 2005
Integrated Circuit Systems, Inc.
ICS87608I
LOW VOLTAGE/LOW SKEW, 1:8 PCI/PCI-X ZERO DELAY CLOCK GENERATOR
REVISION HISTORY SHEET
Rev A A A B b
Table
Page 2 7
Description of Change Corrected MR in the Block Diagram. Parameter Measurement Information - for 3.3V Outpt Load AC Test Circuit diagram corrected GND from "-1.165V5%" to "-1.65V5%". Ordering Information Table - added Lead-Free par t number. AC Characteristics Table - changed tjit(cc) from 120ps max to 170ps max. Feature section, Cycle-to-Cycle Jitter note - added "@ 3.3V".
Date 4/6/04 4/23/04 10/11/04 1/28/05 3/11/05
T10 T7B
11 6 1
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